1. Field of the Invention
The present invention relates to a fabricating method of a semiconductor device such as an insulated gate bipolar transistor (IGBT) or free wheeling diode (FWD) mounted in a power module or the like, and in particular, relates to a semiconductor device fabricating method including in a wafer processing of the semiconductor device a step of grinding the back surface of the wafer in order to obtain a wafer thickness commensurate with the breakdown voltage.
2. Description of the Prior Art
An IGBT, FWD, or the like, mounted in a power module or the like is widely used from commercial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), and switching power supplies to consumer equipment fields such as microwave ovens, rice cookers, and strobe lights. Furthermore, there is a demand from the market to reduce further loss in IGBTs and FWDs, such as reducing on-state voltage, in order to expand the field of application. A fabricating method whereby the thickness of a semiconductor substrate that is thick initially is reduced as far as possible by grinding the wafer from the back surface partway through the wafer processing, within a thickness range allowed by the design breakdown voltage and a fabricating process tolerance range, is known as one effective method of reducing IGBT loss while fabricating with as high production efficiency as possible.
There is a tendency with a power device such as an IGBT or FWD fabricated by a wafer processing according to this kind of fabricating method for the chip thickness (silicon substrate thickness) to be ground ever thinner, within a range that does not cause a decrease in breakdown voltage, in order to improve semiconductor characteristics. A plan view of the whole of a wafer 21 fabricated by this kind of heretofore known wafer processing is shown in FIG. 6, while an enlarged plan array view of the vicinity of a monitor chip region 7a (shown as PCM in FIG. 6) is shown in FIG. 7. A device chip region 3, excluding the monitor chip region 7a, shown in FIGS. 6 and 7 is a region forming a chip of an IGBT, FWD, or the like. Although the monitor chip region 7a cannot be used as a device chip, which is the fabricating object, it is a region used for improving the yield rate by monitoring the wafer processing, is called a process control monitor (PCM), or the like, in the wafer 21, and several are formed in each wafer.
As shown in FIG. 7, electrodes (an IGBT emitter electrode 4, an FWD anode electrode, and the like) formed in an active region 1 in the center of the front surface of the device chip region 3 need a metal film thickness of 3 μm or more, and it is often the case that a protective film (a polyimide resin film 6, or the like, shown by oblique hatching in FIG. 7) formed by coating on an edge region 2 on the periphery of the device chip 3 has a thickness of 10 μm or more. Also, a silicon substrate front surface inside the edge region 2 has a configuration wherein the protective film with a thickness in the region of 10 μm is further deposited on a field plate (not shown) formed of a metal film formed simultaneously with the emitter electrode 4 of the active region 1. Regarding the area ratio over the whole chip, the emitter electrode 4 portion of the active region 1 having no protective film occupies the greater part of the area. Meanwhile, in the monitor chip region 7a, the protective film is applied over the greater part of the region 7a. 
Also, the monitor chip region 7a may be used for applying device (an IGBT or the like) characteristic breakdown tests, such as a measurement of the dielectric strength of a gate oxide film 12 (FIG. 8). Also, by a dielectric formed from the first photolithography step onward after carrying out a depositing of a dielectric using a CVD method being left in the monitor chip region 7a, the monitor chip region 7a may also be used when a problem is discovered in a subsequent step to easily identify the step in which the problem has occurred due to a foreign object, or the like, by analyzing the dielectric left in the monitor chip region 7a. 
Furthermore, as it is possible to carry out cause analysis by analyzing the foreign object, or the like, and thus possible to carry out feedback to the step in which the problem has occurred, there is an advantage in that the cause can be easily eliminated. As a result of this, the reliability of the semiconductor device increases, and defective articles decrease, because of which fabricating yield increases (JP-A-2000-114334 (paragraph 0024)). Furthermore, in addition to the previous description, a photoalignment marker, a test element group (TEG) for monitoring gate breakdown voltage, a PCM for managing trends such as those in oxide film thickness and sheet resistivity, and the like, may be provided in the monitor chip region 7a. Furthermore, a miniature chip or the like may be provided in order to manage electrical characteristics such as on-state voltage (JP-A-2011-216764 (abstract, problems)) or reduce etching variation by managing etching variation (JP-A-2011-86771 (paragraph 0037)).
In the monitor chip region 7a, after a metal film is applied to a thickness of 5 μm over the whole of the wafer by sputter deposition or the like, the metal film is removed by etching, leaving only the metal film in a sensor contact region 10 inside a sensing region 9a shown by a central rectangular frame (broken lines). The lattice form lines inside the sensing region 9a shown in FIG. 7 are the dielectric pattern left for the previously described object. All of the metal film on the outer side of the sensing region 9a is removed by etching. Furthermore, a protective film (a polyimide resin film 6a) of a thickness of 10 μm is applied to the front surface of the sensing region 9a, other than the sensor contact region 10, and an outer side region of the sensing region 9a. Consequently, the monitor chip region 7a has a protruding form with a surface thickness greater than that of the larger part of the device chip region 3 (thickness 5 μm) on the wafer front surface.
With regard to a wafer with this kind of front surface condition, in order to reduce uneven grinding in the wafer plane, which is a problem when grinding the back surface, there is known a method wherein back surface grinding is carried out after the unevenness on the wafer front surface side, which is a caused by the uneven grinding, is aligned to the same level using chemical mechanical polishing (CMP) technology (JP-A-2009-218343 (paragraph 0058)). Furthermore, there is also a document describing a method wherein a thick surface protection tape is attached to the front surface of a semiconductor wafer having irregularities due to a polyimide protective film, and heated to deform the surface protection tape and form a practically even front surface (JP-A-2006-196710 (abstract)).